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february 2010 doc id 15194 rev 2 1/23 23 EMIF06-SD03F3 6-line ipad?, emi filter and esd protection for sd card features esd protection (iec standard) emi filtering level translator signal conditionning integrated power supply with: ? thermal shutdown (tsd) ? under voltage lockout (uvlo) ? short-circuit current limitation (i sc ) ? power on/off feature with enable pin benefits emi low-pass-filter and esd protection (up to 15 kv on external pins) integrated pull up resistors prevent bus floating 50 mhz clock frequency compatible with c line < 40 pf lead-free package in 400 m pitch low power consumption very low pcb space consumption high reliability offered by monolithic integration reduction of parasitic elements thanks to csp integration complies with the following standards: iec 61000-4-2, level 4: external pins ? 15 kv (air discharge) ? 8 kv (contact discharge) hbm iec 61340-3-1: all pins ? 2 kv (air discharge) ? 2 kv (contact discharge) tm: ipad is a trademark of stmicroelectronics. figure 1. pin configuration (bump side) applications removable memory cards in mobile phones, communication systems, and portable applications memory cards compliant with: sd (standard and high speed), minisd, sd and mmc/trans-flash standards description the EMIF06-SD03F3 is a highly integrated device, based on ipad technology, combining the 5 functions described under features . flip chip (24 bumps) a b c d e 1 2 3 4 5 www.st.com
contents EMIF06-SD03F3 2/23 doc id 15194 rev 2 contents 1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 passive integration and low pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 test circuit from host to sd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 test circuit from sd to host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 measurement of t skew (host to sd) from rising edge clk.h . . . . . . . . . . . 12 4.4 measurement of t skew.f (read mode) from rising edge clk.h . . . . . . . . . . 13 5 low drop out voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 line regulation and transient line regulation . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 load regulation and transient load regulation . . . . . . . . . . . . . . . . . . . . . 18 5.3 dropout definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
EMIF06-SD03F3 functional description doc id 15194 rev 2 3/23 1 functional description a side (host-cpu) pin list: v cca , enable, dat123.dir, cmd.dir, cmd.h, clk.h, clk -f, dat0.dir, dat0.h, dat1.h, dat2.h, dat3.h, v bat b side (sd-card) pin list: wp, cd, v ccb , cmd-b, clk-b, dat0-b , dat1-b, dat2-b, dat3-b note: in ta b l e 5 , 6 , 7 , and 10 , collective names are used for groups of pins. the names used are: *.dir = cmd.dir, dat0.dir, dat123.dir *.h = cmd.h, clk.h, dat0.h, dat1.h, dat2.h, dat3.h *-b = cmd-b, clk-b, dat0-b, dat1-b, dat2-b, dat3-b v ia = all a side input pins v ib = all b side input pins. table 1. pin definition pin name bump type side description v cca b3 power input a power supply (1.8v) v ccb b4 power output b power supply (internally generated, 2.9 v) v bat a4 power input a battery power supply gnd c4 ground - ground gnd c3 ground - ground enable c2 input a internal power supply enable cmd.dir a2 input a command direction cmd.h d2 io a a side command clk.h c1 input a clock input clk-f e2 output a clock feedback dat0.dir a3 input a data direction dat0.h d1 io a data host dat123.dir e3 input a data direction dat1.h e1 io a data host dat2.h a1 io a data host dat3.h b1 io a data host wp e4 input to cpu a write protect cd d3 input to cpu a card detect cmd-b d4 io b command direction clk-b c5 output b clock output dat0-b d5 io b data sd dat1-b e5 io b data sd dat2-b a5 io b data sd dat3-b b5 io b data sd
functional description EMIF06-SD03F3 4/23 doc id 15194 rev 2 note: 1 when a side signals direction is input, sd-card is written by cpu-host (i.e b side signals direction is output) when a side signals direction is output, sd -card is read by cpu-host (i.e b side signals direction is input) 2 for b side signals when enable = l: * defined by internal pull-down (see figure 3 for pins cmd.b and data bus dat[0?3].b) figure 2. configuration table 2. function table command signals a side signals direction b si de signal direction enable cmd. dir dat0.dir dat123.dir cmd.h clk.h clk-f dat0.h dat1.h dat2.h dat3.h cmd-b clk-b dat0-b dat1-b dat2-b dat3-b h h x x in in out x x out out x x h l x x out in out x x in out x x h x h x x in out in x x out out x h x l x x in out out x x out in x hx x h xinoutxinxoutxout h x x l x in out x out x out x in l x x x x x z x x l* z l* l* cpu ipad mini sd clk clk vcca 1.8 v vccb vbat cmd cmd cmd cmd dir data 0 - 3 data 0 - 3 esd (15 kv) and emi low drop out voltage regulator dir0 dir1-3 wp, cd esd 2 kv feedback clk
EMIF06-SD03F3 functional description doc id 15194 rev 2 5/23 figure 3. block diagram level-shifters emi filters gnd vccb enable 2kv 500k w ldo ref uvlo otp a r,c vref 15kv 15kv vccb 2kv vcca cmd.h cmd.dir cmd-b 2kv 15kv vccb 15k w 2kv clk-f clk.h clk-b 2kv 15kv 2kv dat0.h dat0.dir dat0-b 2kv 15kv vccb 70k w 2kv dat1.h dat2.h dat3.h dat123.dir dat2-b dat1-b dat3 cd -b 2kv 15kv 2kv 15kv 2kv 15kv 470k w vccb 70k w vccb 70k w 2kv wp 100k w 15kv vcca 100k w 15kv vcca vcca emif06 emif06 - - sd02f3 sd02f3 level-shifters level-shifters emi filters emi filters vccb vccb enable 2kv 500k w enable 2kv 2kv 500k w 500k w ldo ref uvlo otp a r,c vref ref uvlo otp a r,c vref 15kv 15kv 15kv 15kv 15kv vccb 15kv 15kv vccb vccb 2kv vcca 2kv 2kv vcca vcca 2kv 15kv vccb 15k w 2kv 2kv 15kv 15kv vccb 15k w vccb vccb vccb 15k w 2kv 2kv 15kv 2kv 2kv 15kv 15kv 2kv 2kv 15kv vccb 70k w 2kv 2kv 15kv 15kv vccb 70k w vccb vccb vccb 70k w 2kv - 2kv 15kv 2kv 15kv 2kv 15kv 470k w vccb 70k w vccb 70k w 2kv - 2kv 15kv 15kv 2kv 15kv 15kv 2kv 15kv 15kv 470k w 470k w vccb 70k w vccb vccb vccb 70k w vccb 70k w vccb vccb vccb 70k w 2kv 100k w 15kv vcca 100k w 15kv vcca 100k w 15kv vcca vcca 100k w 15kv vcca 100k w 15kv vcca 100k w 15kv vcca vcca vcca vcca vcca emif06 emif06 - - sd02f3 sd02f3 level-shifters emi filters vccb enable 2kv 500k w ldo ref uvlo otp a r,c vref 15kv 15kv vccb 2kv vcca 2kv 15kv vccb 15k w 2kv 2kv 15kv 2kv 2kv 15kv vccb 70k w 2kv - 2kv 15kv 2kv 15kv 2kv 15kv 470k w vccb 70k w vccb 70k w 2kv 100k w 15kv vcca 100k w 15kv vcca vcca emif06 emif06 - - level-shifters - emi filters filters enable enable 2 kv 500 k ldo ref uvlo otp a r,c v ref ref uvlo otp a r,c v bat 2 kv 15 kv v ccb v ccb v ccb v ccb v ccb v ccb v ccb v cca v cca v cca 2 kv v cca 2 kv 15 kv 15 k 2 kv 2 kv 2 kv 15 kv 2 kv 15 kv 70 k 2 kv - 2 kv - 2kv 15 kv 15 kv 2 kv 15 kv 470k r7 70 k r12 r11 r10 r9 r en 70 k 2 kv 100k r14 15kv 100 k r13 15 kv emif06- sd03f3 v cca
characteristics EMIF06-SD03F3 6/23 doc id 15194 rev 2 2 characteristics table 3. absolute maximum ratings symbol parameter value unit esd a side (host-cpu) all pins: hbm iec61340-3-1 v cca , enable, dat123.dir, cmd.dir, cmd.h, clk.h, clk -f, dat0.dir, dat0.h, dat1.h, dat2.h , dat3.h, v bat b side (sd-card) external pins : iec 61000-4-2, level 4 v ccb , cmd-b, clk-b, dat0-b, dat1-b, dat2-b, dat3-b, wp, cd air discharge contact discharge air discharge contact discharge 2 2 15 8 kv t jmax maximum junction temperature 150 c r th (j-a) (1) thermal resistance from junction to ambient board: epoxy fr4, copper thickness = 40 m, 4 layers 64 c/ w p dmax maximum power dissipation: p dmax = (t jmax - t aopmax )/ rth (j-a) 1w t stg storage temperature range -55 to +150 c voltage v bat , v ccb , enable -0.3 to 5.5v v cmd-b, clk-b, dat0-b, dat1-b , dat2-b, dat3-b -0.3 to v ccb + 0.3 v cca -0.3 to 3.3 dat123.dir, cmd.dir, cmd.h, clk.h, cl k -f, dat0.dir, dat0 .h, dat1.h, dat2.h, dat3.h, wp, cd -0.3 to v cca +0.3 1. v ccb is an internally generated power suppl y, no external voltage should be applied on this pin other than a current clamp. the thermal resistance depends on printed circuit board layout. to di ssipate the heat efficiently away from flip chip bumps, it is better to make copper planes the largest po ssible as well as consi dering thermal vias usage.
EMIF06-SD03F3 characteristics doc id 15194 rev 2 7/23 table 4. recommended operating conditions symbol parameter conditions min. typ. max. unit v cca power supply 1.62 1.8 1.92 v v bat battery power supply 3.1 - 5 v i out v ccb output current 0.10 100 200 ma c bat external battery capacitance ceramic capacitor - 2.20 - f c out (1) external output capacitance t a = -40 c to +85 c, v bias = 0 v to 3.3 v multi-layer ceramic capacitor type like: c20rx7r1c225k 1.4 (-35%) 2.20 3.0 (+35%) f esr (2) equivalent series resistance for c out f = 1 hz to 10 mhz multi-layer ceramic capacitor type like: c2012x7r1c225kt -3200m t aop ambient operating temperature -30 25 85 c t jop juntion operating temperature -30 25 125 c p dop maximum power dissipation p dop = (t jop - t aop )/r th (j-a) --625mw enable enable input voltage 0 - v cca v external pins (without wp and cd) cmd-b, clk-b, dat0-b, dat1-b, dat2-b, dat3-b 0 - v ccb v internal pins (except enable, with wp and cd) wp, cd, dat123.dir, cmd.dir, cmd.h, clk.h, clk-f, dat0.dir, dat0.h , dat1.h, dat2.h, dat3.h 0-v cca v 1. c out = 2.2 f is minimum allowable capac itance value to guarantee ldo stability 2. values for esr include the v ccb - c out resistance path and c out - gnd resistance path. these resistance paths need to be minimized in pcb design.
passive integration and low pass filter EMIF06-SD03F3 8/23 doc id 15194 rev 2 3 passive integration and low pass filter figure 4. circuit diagram of EMIF06-SD03F3 (without ldo) note: v br in 14 v technology for pins: cmd-b, clk- b, dat0-b, dat1-b, dat2-b, dat3-b, wp, cd v br in 8 v technology for pins: vcc-b, clk.h, clk-f, cmd.h, dat0.h, dat1.h, dat2.h, dat3.h table 5. ldo - current levels in recommended operating conditions symbol parameter test conditions (1) min. typ. max. unit i q_off quiescent current consumption i cca _off v en = 0.4 v, v bat = 3.4 v, v cca = 1.92 v *.dir, *.h, *-b = gnd, wp = cd = v cca all other pins floating --1a quiescent current consumption i bat _off v en = 0.4 v, v bat = 5 v, v cca = 1.92 v *.dir, *.h, *-b = gnd all other pins floating --1a i q_on quiescent current consumption (ground pin current) i bat + i cca level shifter disactivated *.dir = 0 v, v bat = 3.4 v v en = v cca = v clk.h = 1.8 v all other pins floating i out = 100 a - 160 220 a i out = 50 ma - 320 375 a i out = 100 ma - 470 550 a i out = 200 ma - 750 900 a 1. see note: on page 3 for definition of collective names of pins, for example *.dir table 6. level shifter - current levels in recommended operating conditions symbol parameter test conditions (1) min. typ. max. unit i cca _on quiescent current on v cca v en = v cca = 1.92 v, v bat = 3.4 v *.dir = v cca , via = *.h = v cca -310a i ccb _on quiescent current on v ccb v en = v cca = 1.92 v, v bat = 3.4 v *.dir = 0 v, v ccb = 3.05 v, vib = v ccb -1530a 1. see note: on page 3 for definition of collective names of pins, for example *.dir gnd gnd gnd gnd 15 kv 15 kv 15 kv 15 kv card side host side level shifter r2 r4 r6 r5 r3 r1 r12 r7 r en r14 r13 r11 r10 r9 clk b clk.h cmd b cmd.h data0 b data0.h data1 b data1.h data2 b data2.h wp data3 b esd 15 kv esd 15 kv data3.h enable vcca vccb cd esd 2 kv
EMIF06-SD03F3 passive integration and low pass filter doc id 15194 rev 2 9/23 table 7. components symbol parameter test conditions (1) min. typ. max. unit c in-a input capacitance for a side v bat = 3.4 v, *.dir = v en = v cca f = 1 mhz, v dc = 0 v, 30 mv, v ac = 30mv -510pf c in-b input capacitance for b side v bat = 3.4 v, *.dir = gnd, v en = v cca f = 1 mhz, v dc = 0 v, 30 mv, v ac = 30mv -2535pf c emif capacitance seen on b side from emif filter - 15 - pf r1, r2, r3, r4, r5, r6 (2) emif resistors (3) t j = 25 c - 40 - r line line resistance at 20 ma 40 50 60 r10, r11, r12 emif resistors (4) t j = 25 c 49 70 91 k r9 emif resistor (4) t j = 25 c 10.5 15 19.5 k r7 emif resistor (4) t j = 25 c 329 470 611 k r13 emif resistor (4) t j = 25 c 70 100 130 k r14 emif resistor (4) t j = 25 c 70 100 130 k r en resistor (4) t j = 25 c - 500 - k 1. see note: on page 3 for definition of collective names of pins, for example *.dir 2. these values are guaranteed by design and statistical process control. 3. 20% tolerance in resistance value 4. 30% tolerance in resistance value figure 5. frequency response with level shifters internally bypassed (1) 1. measurement in 50 environment figure 6. crosstalk response with level shifters internally bypassed (1) 100.0k 1.0m 10.0m 100.0m 1.0g - 30.00 - 25.00 - 20.00 - 15.00 - 10.00 - 5.00 0.00 db f/hz a1- a5 b1- b5 c1 - c5 d1- d5 e1- e5 f (hz) 100.0k 1.0m 10.0m 100.0m 1.0g - 120.00 - 100.00 - 80.00 - 60.00 - 40.00 - 20.00 0.00 a1- b5 c1 - d5 d1- e5 f (hz) db
data transmission EMIF06-SD03F3 10/23 doc id 15194 rev 2 4 data transmission all values in the tables below are guaranteed across the operating temperature and voltage range unless otherwise specified. table 8. dc voltage levels on host side symbol parameter test conditions min. typ. max. unit v iha high level input voltage 0.65 x v cca v cca -v v ila low level input voltage 0 0 0.35 x v cca v v oha high level output voltage i oh = -6 ma v cca - 0.45 - - v v ola low level output voltage i ol = 7 ma - 0 0.45 v table 9. dc voltage levels on sd side symbol parameter test conditions min. typ. max. unit v ihb high level input voltage 0.7 x v ccb (1) 1. v ccb is defined in power supply block. v ccb -v v ilb low level input voltage - 0 0.3 x v ccb (1) v v ohb high level output voltage i oh = -8 ma v ccb (1) - 0.7 2.9 - v v olb low voltage output voltage i ol = 8 ma - 0 0.7 v table 10. dc current levels symbol parameter test conditions (1) 1. see note: on page 3 for definition of collective names of pins, for example *.dir min. typ. max. unit i lh leakage current on host pin v en = *.dir = v cca = 1.92 v, v ia = v cca or gnd, v bat = 3.4 v --5a i lsd leakage current on sd pin v bat = 3.4 v, v clk.h = v cca , v cmd = v dat0 = v dat1 = v dat2 = v ccb v dat3 = *.dir = gnd --5a i sch short circuit current on host side sd input = h, host= 0 v sd input = 0 v, host = v cca = 1.8 v *.dir = 0 v, v bat = 3.4 v, t j = 25 c -25 -ma i scsd short circuit current on sd side host input = h, sd = 0 v host input= l, sd = v ccb , t j = 25 c *.dir = v cca = 1.8 v, v bat = 3.4 v -60 -ma
EMIF06-SD03F3 data transmission doc id 15194 rev 2 11/23 figure 7. symbol definitions of t plh , t phl , t r and t f for ac characteristics in table 11 4.1 test circuit from host to sd test circuit from host to sd is shown in figure 8 . timings are measured for the whole line cell (shifter + emi + esd) on an external load c sd = 15 pf (board capacitance 5 pf + sd card capacitance 10 pf). figure 8. test circuit from host to sd table 11. ac characteristics (1) 1. t aop -30 to 85 c, i out = 1 ma, c bat = 2.2 f, c out = 2.2 f symbol parameter test cond itions min. typ. max. unit t phl propagation delay hl from host to sd section 4.1 -3.56 ns t plh propagation delay lh from host to sd - 3.5 6 t phl propagation delay hl from sd to host section 4.2 -36 ns t plh propagation delay lh from sd to host - 3 6 t r rise time from host to sd section 4.1 -1.53 ns rise time from sd to host section 4.2 -0.52 t f fall time from host to sd section 4.1 -1.93 ns fall time from sd to host section 4.2 -0.52 t skew delay differences from host to sd section 4.1 , section 4.3 -1.0 0 1.0 ns t skew.f t skew delay from sd to host section 4.2 , section 4.4 -1.5 0 1.5 ns t p_clkf propagation delay for clk feedback - 6.5 12 ns t r_clkf rise time for clk feedback section 4.2 -0.52 ns t f_clkf fall time for clk feedback section 4.2 -0.52 ns input 0v 0v vorv cca ccb vorv cca ccb output 70% 20% 20% 50% 50% 50% 50% t plh t r t f t phl 70% host sd c sd =15 pf
data transmission EMIF06-SD03F3 12/23 doc id 15194 rev 2 4.2 test circuit from sd to host test circuit from sd to host is shown in figure 9 . timings are measured for the whole line cell (shifter + emi + esd) on an external load c host = 5 pf (board capacitance + host capacitance). figure 9. test circuit from sd to host 4.3 measurement of t skew (host to sd) from rising edge clk.h figure 10. example of measurement of t skew (host to sd) from ri sing edge of clk.h host sd c host = 5 pf t skew = tp(clk.h clk.h tp(clk.h clk clk clk - - - b) b b) - tp(datx.h dat.h tp(datx.h datx dat datx - x- - b) b b) minisd card cpu emif06-sd02f3 clk-b 15pf clk.h = ? 1 ? 15pf minisd card cpu EMIF06-SD03F3 clk-b dat-b 15pf 15pf dat.dir = ? 1 ? clk.f dat.h 15pf 15pf 0v 0v 0v 0v v ccb v ccb v cca v cca 50% 50% 50% 50%
EMIF06-SD03F3 data transmission doc id 15194 rev 2 13/23 4.4 measurement of t skew.f (read mode) from rising edge clk.h figure 11. example of measurement of t skew.f for read mode from rising edge of clk.h datx.h = dat0.h, dat1.h, dat2.h, dat3.h, cmd.h datx-b = dat0-b, dat1-b, dat2-b, dat3-b, cmd.b cpu EMIF06-SD03F3 t skew.f = tp ( tp ( clk.h clk.h clk. clk. clk. clk. f f h f ) ) ?[ tp(clk.h clk -b) + tp(datx-b datx.h) ] 5pf clk-b dat-b 15pf clk.h dat.dir = ? 0 ? clk.f delay dat.h 5pf minisd card tp(clk.h clk clk - - b b) 0v 0v v ccb v cca v cca 50% 50% 50% datx-b tp(datx-b datx datx .h .h) 0v 0v 0v v cca v ccb 50% 50%
low drop out voltage regulator EMIF06-SD03F3 14/23 doc id 15194 rev 2 5 low drop out voltage regulator figure 12. low drop out voltage regulator cout mini-sd card base band asic cbat bat cvcca a vbat vccb 15kv + - r,c 2kv vref uvlo tsd en 2kv logic gnd ls vcca vbat vcca vcca vbat vccb ven gnd power management asic emif06-sd02f3 (ldo part only) c out mini-sd card base band asic bat c bat bat c vcca a vbat vccb 15kv + - r,c 2kv vref uvlo tsd en 2kv logic gnd ls vcca vbat vcca a v bat v ccb 15 kv + - r,c 2 kv v ref uvlo tsd en 2 kv 500 k r eq = 135 logic gnd level shifter v cca v bat v cca v cca v bat v ccb v en r en gnd power management asic EMIF06-SD03F3 (ldo part only)
EMIF06-SD03F3 low drop out voltage regulator doc id 15194 rev 2 15/23 table 12. static parameters, v en = v cca unless otherwise specified (1) symbol parameter test conditions min. typ. max. unit v out regulated output voltage (v ccb ) v bat = 3.4 v, i out = 100 ma, t j = 25 c 2.81 (-3%) 2.90 2.99 (+3%) v v bat = 3.4 v, i out = 100 ma, t j = -30 to 125 c 2.81 (-3%) - 2.99 (+3%) v v bat = 3.1 to 5 v, i out = 0.1 to 200 ma, t j = -30 to 125 c 2.75 (-5%) - 3.05 (+5%) v lir line regulation v bat = 3.4 to 5 v ( section 5.1 ), i out = 100 ma, t j = 25 c -320mv ldr load regulation v bat = 3.4 v, i out = 1 to 200 ma ( section 5.2 ), t j = 25 c -50100mv v do dropout voltage v out (nom) - 100 mv ( section 5.3 ), t j = -30 to 85 c i out = 50 ma - 25 37 mv i out = 100 ma - 50 75 mv i out = 200 ma - 100 150 mv i sc short circuit current limitation v bat = 5 v, v out = 0 v, t j = 25 c - 500 - ma tsd thermal shutdown temperature v bat = 3.4 v shutdown (temp ) - 150 - c reset (temp ) - 130 - c hysteresis - 20 - c uvlo under voltage lockout t j = -30 to 125 c shutdown (v bat ) 2.3 2.5 2.7 v reset (v bat ) 2.35 2.55 2.75 v hysteresis - 50 - mv 1. level shifter disactivated, *.dir = 0, clk.h = v cca , all other pins floating.
low drop out voltage regulator EMIF06-SD03F3 16/23 doc id 15194 rev 2 table 13. dynamic parameters (v en = v cca unless otherwise specified) symbol parameter test conditions min. typ. max. unit litr line transient peak voltage v bat = 3.4 v 4 v, t tr = 30 s, i out = 200 ma t j = 25 c ( section 5.1 ) c out = 2.2 f, esr = 5 m -4.2 -mv ldtr load transient peak voltage i out = 1 ma 200 ma, t tr = 10 s, v bat = 3.4 v t j = 25 c ( section 5.2 ) c out = 2.2 f, esr = 5 m -9 -mv psrr power supply rejection ratio v bat = 3.4 v, i out = 100 ma, t j = 25 c, c out = 2.2 f, esr = 5 m f = 1 khz - 45 - db f = 10 khz - 35 - db t start settling time v out 95% nom, v bat = 5 v, i out = 200 ma t j = -30 c to 125 c, c out = 2.2 f, enable l h - 30 200 s t stop discharge time v out 10% nom, v bat = 3.4 v, i out = 1 ma t j = 25 c, c out = 2.2 f, enable h l -600 - s
EMIF06-SD03F3 low drop out voltage regulator doc id 15194 rev 2 17/23 5.1 line regulation and transient line regulation the line regulation (lir) is a static variable that indicates the change in the output voltage of the voltage controller v out (at constant load) when there is a change v bat at the input voltage. by contrast the line transient response (litr) represents dynamic peak value to be observed during the change in input voltage thermal effects due to changes in the junction temperature are circumvented with pulsed voltage during the test and are to be taken into account separately. the figure shows the boundary conditions for t rise , t fall , and v bat to be taken as the basis of the measurement of the line transient response without additional decoupling of the supply voltage by a buffer capacity c bat . the values defined in the specification apply, however, only in the case of decoupling of the supply voltage with such a capacity c bat , as a result of which the values for t rise and t fall are influenced to some extent. figure 13. line regulation and transient line regulation time t fall = t tr t rise = t tr vrise lir time line regulation: lir=f(vbath,vbatl) line transient: litr = max( vfall static and dynamic line regulation vbatl vbath vbat vout vrise, vfall) ?lir(vbath,vbatl) 4v 3.4 v vbat x: 0.2 ms/div y: 100 mv/div x: 0.2 ms/div y: 4 mv/div vout transient line regulation measurement typcial values at 25 c temperature ( c) 0 1 2 3 4 5 -10 25 85 lir (mv) litr (mv) line regulation (lir) and line transient (litr) versus temperature (typical values
low drop out voltage regulator EMIF06-SD03F3 18/23 doc id 15194 rev 2 5.2 load regulation and transient load regulation the load regulation (ldr) is a static variable that indicates the change in output voltage of the voltage controllor v out (at constant input voltage) in the event of a change in the load current i out . by contrast the load transient respon se (ldtr) represents the dynamic peak value to be observed during load variation. thermal effects due to changes in the junction temperature are circumvented by testing with pulsed load and are to be taken into account separately. the figure shows the boundary conditions for t rise , t fall , and i out to be taken as the basis for the measurement of the load transient response. figure 14. load regulation and tr ansient load regulation time t rise = t tr t fall = t tr vrise ldr time vfall static and dynamic load regulation ioutl iouth load regulation: ldr=f(iouth,ioutl) load transient: ldtr = max( vrise, vfall) ?ldr(iouth,ioutl) iout vout x: 50s/div y: 50ma/div x: 50s/div y: 10mv/div iout vccb transient load regulation measurement (typical values at 25 c) temperature ( c) 0 10 20 30 40 50 60 -10 25 85 ldr (mv) ldtr (mv) load regulation (ldr) and load transient (ldtr) versus temperature (typical values
EMIF06-SD03F3 application schematic doc id 15194 rev 2 19/23 5.3 dropout definition the dropout voltage (v do ) is measured by decreasing th e input voltage till the output voltage will drop by 100 mv compared to th e output volta ge measured at the specified minimum supply voltage (3.1 v). worst case for dropout is maximum die temperature and maximum current load. this is done statically. figure 15. dropout definition 6 application schematic figure 16. application schematic v(vout) v(vbat) vdo 100 mv 2.888e+00 2.873e+00 3.100e+00 2.772e+00 2.888e+00 -2.122e-01 3.100e+00 base cmd dir 2 1 9 7 8 5 4 3 6 cmd dat3/cd/cs dat2 dat0 dat1 clk vdd vss1 vss2 1.8 v cout 3 b4 a4 b3 12 a2 d2 c1 c1 a3 d1 e3 e1 b1 26 36 a1 12 10 c4 c3 d3 e4 dat0 -b vccb vbat vcca dat1 -b cmd.dir cmd.h clk.h clk.f dat0.dir dat0.h dat123.dir dat1.h dat3.h cmd-b clk-b dat2.h dat2 -b dat3 -b gnd gnd cd wp clk feedback cmd cbat data 0 - 3 vbat data dir cvcca clk c2 enable enable 3.0 v EMIF06-SD03F3
ordering information scheme EMIF06-SD03F3 20/23 doc id 15194 rev 2 7 ordering information scheme figure 17. ordering information scheme 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 18. flip chip dimensions emif yy - xx zz f 3 emi filter number of lines information package x = resistance value (ohm) z = capacitance value / 10 (pf) or 2 letters = application 2 digits = version f = flip chip 3 = lead-free, pitch = 400 m 605 m 55 2.1 mm 30 m 2.1 mm 30 m 255 m 40 400 m 40 400 m 40
EMIF06-SD03F3 ordering information doc id 15194 rev 2 21/23 figure 21. flip chip tape and reel specifications 9 ordering information note: more information is availa ble in the application notes: an2348 :"flip chip : package description and recommendations for use" an1751 : emi filters: recommendations and measurements figure 19. footprint recommendations figure 20. marking 220 m recommended 220 m recommended 260 m maximum solder stencil opening : copper pad diameter: solder mask opening: 300 m minimum x y x w z w dot, st logo ecopack status xx = marking yww = datecode (y = year ww = week) z = manufacturing location dot identifying pin a1 location user direction of unreeling all dimensions in mm 4.0 0.1 4.0 0.1 2.0 0.05 8.0 0.3 1.75 0.1 3.5 0.1 ? 1.55 0.1 0.69 0.05 2.25 0.20 0.02 xxz xxz xxz 2.25 st st st yww yww yww table 14. ordering information order code marking package weight base qty delivery mode EMIF06-SD03F3 hy flip chip 5.46 mg 5000 tape and reel (7?)
revision history EMIF06-SD03F3 22/23 doc id 15194 rev 2 10 revision history table 15. document revision history date revision changes 21-nov-2008 1 first issue 11-feb-2010 2 ac timing characteristics updated in ta b l e 1 1 .
EMIF06-SD03F3 doc id 15194 rev 2 23/23 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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